1. Field of the Invention
The invention relates to a test method for integrated circuit of semiconductor memory device under wafer-level-burn-in, and more particularly the test method will be employed in dynamic random access memory (DRAM) fabrication process.
2. Description of the Prior Art
Generally, semiconductor memory devices are tested by checking whether the intended data can be obtained for input of a particular address signal, thereby distinguishing between good and bad ones. Such as FIG. 1, it illustrates wafer-level-burn-in circuitry example of the experimental dynamic random access memory (DRAM). It will be mentioned that as FIG. 1, the system according to the prior art is schematically shown to include a plurality of word line, such as WL.sub.1, WL.sub.2, WL.sub.3, WL.sub.4, WL.sub.5, . . . to WL.sub.n a word line driver 101, a sense amplifier 102, bit line (BL, BL) respectively. Some small transistors are implemented at each word line edge to simultaneously apply the stress bias to the transfer gates, especially by probing the corresponding test pads. Thus in the past few years, as the above figure shown, the DRAM under wafer-level-burn-in is stressed to word-line and bit-line, respectively. However, unfortunately this cannot be achieved the stress for the effect of cell-to-cell and cell-to-bit-line. Also, the test mode will be executed after all fabrication process completed.
As a matter of fact, in recent years, with advances in miniaturization techniques, the memory cell area has been further reduced. According to the above statement, which in turn has led to an increase in the failure rate attributed to short circuits between adjacent word lines or between adjacent bit lines within the memory array due to processing effects. Therefore, according to the conventional technology, verification of failure has been accomplished by sequentially reading every address location and thus determining the result. However, verification methods have the disadvantage of requiring a test period, which even further increases with the increase of the memory capacity being expanded. Certainly, it is important that spurious indications of defects should not be given. Therefore the testing result contains, in addition to the force cell device and the compared cell device. The cell device identifies digits of the serial checking vectors as to which no determination of correctness should be made.